1. Field of the Invention
This invention relates to a dynamic semiconductor memory device (DRAM).
2. Description of the Related Art
A DRAM having a memory cell array which is constructed by forming a plurality of NAND memory cell units each of which is constructed by a plurality of series-connected memory cells and connecting a plurality of memory cell units to bit lines is known in the prior art. In this memory cell array system, the number of bit line contacts can be made small in comparison with a system in which memory cells are individually connected to bit lines and therefore the cell area can be reduced.
With the above NAND cell array system, when data is read out from a memory cell of the memory cell unit which lies at a long distance from the bit line, data of memory cell or cells lying between the readout memory cell and the bit line must be destroyed. Therefore, it becomes necessary to use a register for temporarily holding the data of the memory cell unit and re-write the data (for example, refer to IEEE ISSCC DIGEST OF TECHNICAL PAPERS, VOL. 34, p106, TAM.2, 1991).
As the layout method for the above temporary storing register, a method of commonly using a register for a plurality of memory cell arrays is provided. In this method, a global bit line is arranged to cross a plurality of memory cell arrays, nodes of a plurality of sense amplifiers are connected to the global bit lines via transfer gates and a register is connected to one end of the global bit line.
However, in the above conventional system, it is necessary to charge and discharge the global bit line which has a larger capacitance than the bit line arranged in the memory cell array in order to re-write data which is temporarily stored in the register. Therefore, in the conventional DRAM, the power consumption in the data re-writing operation is large.
In the above NAND cell array system, since the cell area is small, the open bit line system may be effectively used. Therefore, in the cell array system, a pseudo-folded bit line system which is a modification of the open bit line system is proposed. This system is a system in which a dummy cell array arranged at the end portion of the memory block is commonly used by memory cell arrays in the memory block.
However, in this system, it is necessary to construct the dummy cell array by memory cell units each formed of a plurality of series-connected dummy cells in the same manner as in the memory cell array and therefore the area of the dummy cell array becomes large.
In the conventional ordinary DRAM in which each memory cell is connected to a corresponding one of bit line contacts, the operation of writing data into a memory cell from the exterior of the chip is effected at the same time of effecting the active restoring operation in which data is read out from a memory cell to a bit line pair, a potential difference is amplified to Vcc and Vss by a sense amplifier, data is transferred to a DQ line, and then data is re-written into the memory cell.
In the above system, the readout mode and write-in mode of the DRAM are not separated from each other and it is not necessary to provide a circuit for setting the mode. However, in this method, when data is read out from the memory cell to the bit line pair and data set in an inverted relation with respect to data obtained by amplifying a potential difference between Vcc and Vss by use of the sense amplifier is written from the exterior, the operation is active, and since the potentials Vcc and Vss on the two nodes of the sense amplifier for amplifying data from the memory cell to the potential difference between Vcc and Vss must be inverted to Vss and Vcc, respectively, the power consumption becomes large.
In addition, in the DRAM in which a memory cell unit formed of series-connected memory cells is connected to a bit line, the memory cells are serially connected so that data of the memory cells cannot be read out at random and at a high speed.
As described above, in the conventional DRAM in which a NAND memory cell unit is constructed by serially connecting a plurality of memory cells, it is necessary to charge and discharge the global bit line in order to re-write data and the power consumption becomes large. In the case of using the pseudo-folded bit line system, the cell area of the conventional DRAM is increased by an amount corresponding to the dummy cell array. Further, the memory cells are serially connected in the conventional DRAM, data of the memory cells cannot be read out at random and at a high speed.
In an ordinary DRAM in which each memory cell is connected to a corresponding one of bit line contacts, when data is written into the memory cells and data set in an inverted relation with respect to data obtained by amplifying a potential difference to Vcc and Vss by use of the sense amplifier is written from the exterior, the operation is active, and since the potentials Vcc and Vss on the two nodes of the sense amplifier for amplifying data from the memory cell to the potential difference between Vcc and Vss must be inverted to Vss and Vcc, respectively, the power consumption becomes large.
In a dynamic semiconductor memory device, a sense amplifier is connected to a pair of bit lines from which data is read out in response to the selection of one word line. In recent years, however, memory cells have to be installed in a narrow area, and sense amplifiers for the respective pairs of bit lines cannot be easily arranged.
As described above, for example, in the open bit line system, it is difficult to lay out the sense amplifiers.